2. ABC RFET Mapper: ABC Technology Mapper for Reconfigurable FET based circuits

ABC RFET Mapper is an area-optimized technology mapping which uses the innate reconfigurability, offered by SiNW transistors for efficient circuit designs.

In case of usage of our methodology, please refer to our corresponding DATE-18 paper:

Rai, M. Raitza and A. Kumar, "Technology mapping flow for emerging reconfigurable silicon nanowire transistors," 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2018, pp. 767-772. doi: 10.23919/DATE.2018.8342110

For queries please contact Prof. Dr. Akash Kumar or Shubham Rai.

Library Download Link

3. RFET Synthesis Design Flow

This is a complete design flow, including both logic and physical synthesis, for circuits based on SiNW RFETs. We propose layouts of logic gates, Liberty and LEF (Library Exchange Format) files to enable further research in the domain of these novel, functionally enhanced transistors.

In case of usage of our methodology, please refer to our corresponding DATE-18 paper:

Rai et al., "A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs," 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2018, pp. 605-608. doi: 10.23919/DATE.2018.8342080

For queries please contact Prof. Dr. Akash Kumar or Shubham Rai.

Design Flow Download Link

4. Reloc: An Open-Sourced Vivado Workflow for Generating Relocatable, Out-Of-Context End-User Configuration Tiles

The latest repository of the workflow can be downloaded from Here. 

5. Area-Optimized Low-Latency Approximate Multipliers for FPGA-based Hardware Accelerators

We provide a novel approximate multiplier architecture customized towards the FPGA-based fabrics, an efficient design methodology, and an open-source library.

In case of usage of our approximate multipliers, please refer to our corresponding DAC-18 paper: 

Salim Ullah, Semeen Rehman, Bharath Srinivas Prabakaran, Florian Kriebel, Muhammad Abdullah Hanif, Muhammad Shafique, and Akash Kumar. 2018. Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators. In Proceedings of the 55th Annual Design Automation Conference (DAC '18). ACM, New York, NY, USA, Article 159, 6 pages. DOI: https://doi.org/10.1145/3195970.3195996

For queries please contact Prof. Dr. Akash Kumar or Salim Ullah.

Open-source Library Download

6. SMApproxLib: Library of FPGA-based Approximate Multipliers

SMApproxLib is an open-source library of approximate multipliers with different bit-widths, output accuracies and performance gains. For each n×n accurate multiplier, we provide three approximate n×n multiplier designs by efficient utilization of LUTs and carry chains.

In case of usage of our approximate multipliers, please refer to our corresponding DAC-18 paper: 

Salim Ullah, Sanjeev Sripadraj Murthy, and Akash Kumar. 2018. SMApproxlib: library of FPGA-based approximate multipliers. In Proceedings of the 55th Annual Design Automation Conference (DAC '18). ACM, New York, NY, USA, Article 157, 6 pages. DOI: https://doi.org/10.1145/3195970.3196115

For queries please contact Prof. Dr. Akash Kumar or Salim Ullah.

Open-source Library Download: Main, Sim1, Sim2, Sim3, Sim4, Sim5, Sim6

7. Accurate and Approximate Softcore Signed Multiplier Architectures

The article related to the library "Area-optimized Accurate and Approximate Softcore Signed Multiplier Architectures" is currently under review. The RTL and Behavioral models of the multipliers can be provided on request.

For queries please contact Prof. Dr. Akash Kumar or Salim Ullah.