1. DeMAS: Library of Approximate Adders
DeMAS is an open-source design methodology for synthesizing and implement approximate adders for any FPGA-based system by considering the underlying resources and architectural differences.
In case of usage of our methodology, please refer to our corresponding DATE-18 paper:
S. Prabakaran et al., "DeMAS: An efficient design methodology for building approximate adders for FPGA-based systems," 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2018, pp. 917-920. doi: 10.23919/DATE.2018.8342140
2. ABC RFET Mapper: ABC Technology Mapper for Reconfigurable FET based circuits
ABC RFET Mapper is an area-optimized technology mapping which uses the innate reconfigurability, offered by SiNW transistors for efficient circuit designs.
In case of usage of our methodology, please refer to our corresponding DATE-18 paper:
Rai, M. Raitza and A. Kumar, "Technology mapping flow for emerging reconfigurable silicon nanowire transistors," 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2018, pp. 767-772. doi: 10.23919/DATE.2018.8342110
For queries please contact Prof. Dr. Akash Kumar or Shubham Rai.
3. RFET Synthesis Design Flow
This is a complete design flow, including both logic and physical synthesis, for circuits based on SiNW RFETs. We propose layouts of logic gates, Liberty and LEF (Library Exchange Format) files to enable further research in the domain of these novel, functionally enhanced transistors.
In case of usage of our methodology, please refer to our corresponding DATE-18 paper:
Rai et al., "A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs," 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2018, pp. 605-608. doi: 10.23919/DATE.2018.8342080
For queries please contact Prof. Dr. Akash Kumar or Shubham Rai.
4. Reloc: An Open-Sourced Vivado Workflow for Generating Relocatable, Out-Of-Context End-User Configuration Tiles
The latest repository of the workflow can be downloaded from Here.
5. Area-Optimized Low-Latency Approximate Multipliers for FPGA-based Hardware Accelerators
We provide a novel approximate multiplier architecture customized towards the FPGA-based fabrics, an efficient design methodology, and an open-source library.
In case of usage of our approximate multipliers, please refer to our corresponding DAC-18 paper:
Salim Ullah, Semeen Rehman, Bharath Srinivas Prabakaran, Florian Kriebel, Muhammad Abdullah Hanif, Muhammad Shafique, and Akash Kumar. 2018. Area-optimized low-latency approximate multipliers for FPGA-based hardware accelerators. In Proceedings of the 55th Annual Design Automation Conference (DAC '18). ACM, New York, NY, USA, Article 159, 6 pages. DOI: https://doi.org/10.1145/3195970.3195996
For queries please contact Prof. Dr. Akash Kumar or Salim Ullah.
6. SMApproxLib: Library of FPGA-based Approximate Multipliers
SMApproxLib is an open-source library of approximate multipliers with different bit-widths, output accuracies and performance gains. For each n×n accurate multiplier, we provide three approximate n×n multiplier designs by efficient utilization of LUTs and carry chains.
In case of usage of our approximate multipliers, please refer to our corresponding DAC-18 paper:
Salim Ullah, Sanjeev Sripadraj Murthy, and Akash Kumar. 2018. SMApproxlib: library of FPGA-based approximate multipliers. In Proceedings of the 55th Annual Design Automation Conference (DAC '18). ACM, New York, NY, USA, Article 157, 6 pages. DOI: https://doi.org/10.1145/3195970.3196115
For queries please contact Prof. Dr. Akash Kumar or Salim Ullah.
Open-source Library Download: Main, Sim1, Sim2, Sim3, Sim4, Sim5, Sim6
7. Accurate and Approximate Softcore Signed Multiplier Architectures
If you use this library in your work, please cite the following paper:
S. Ullah, H. Schmidl, S. S. Sahoo, S. Rehman and A. Kumar, "Area-Optimized Accurate and Approximate Softcore Signed Multiplier Architectures," in IEEE Transactions on Computers, vol. 70, no. 3, pp. 384-392, 1 March 2021, doi: 10.1109/TC.2020.2988404.
@ARTICLE{9072581,
author={Ullah, Salim and Schmidl, Hendrik and Sahoo, Siva Satyendra and Rehman, Semeen and Kumar, Akash},
journal={IEEE Transactions on Computers},
title={Area-Optimized Accurate and Approximate Softcore Signed Multiplier Architectures},
year={2021},
volume={70},
number={3},
pages={384-392},
doi={10.1109/TC.2020.2988404}}
For queries please contact Prof. Dr. Akash Kumar or Salim Ullah.
8. Hardware Watermarking Tool for Reconfigurable Nanotechnologies
The tool embeds the signature of a designer in his IP design such that all instances of the final IC carry this signature as a watermark. This may prove useful in case the designer wants to contest against fake/counterfeited/overbuilt/pirated copies of his own IP.
More details can be found in our ISVLSI'19 paper:
Rai S, Rupani A, Nath P, Kumar A. "Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable Nanotechnologies". In Proceedings of the ISVLSI'19. IEEE, Miami, FL, USA
In case of any issues, contact: Ansh Rupani (ansh.rupani@tu-dresden.de)
9. A Partial-Reconfiguration-Enabled HW/SW Co-Design Benchmark for LTE Applications
This is an open-source benchmark developed for LTE applications, in particular the WiBench and Phy-Bench benchmarks.
More details can be found in our paper below. Please cite the paper below when using this library.
Ali Hosseinghorban, Akash Kumar, "A Partial-Reconfiguration-Enabled HW/SW Co-Design Benchmark for LTE Applications", In Electronics, vol. 11, no. 7, 2022. [doi]
@Article{ali-mdpi-electronics-2022,
AUTHOR = {Ali Hosseinghorban and Akash Kumar},
TITLE = {A Partial-Reconfiguration-Enabled HW/SW Co-Design Benchmark for LTE Applications},
JOURNAL = {Electronics},
VOLUME = {11},
YEAR = {2022},
NUMBER = {7},
ARTICLE-NUMBER = {978},
URL = {https://www.mdpi.com/2079-9292/11/7/978},
ISSN = {2079-9292},
DOI = {10.3390/electronics11070978}
}