1. ScaDS.AI: Robust and Low-Power Machine Learning at the Edge (more information).



2. X-DNet: Energy-Efficient Distributed and In-Network Computing via Approximation of Applications and Accelerators



3. X-ReAp: Cross(X)-Layer Runtime Reconfigurable Approximate Architecture (more information, Extension of ReAp-DFG-2018).


4. Re-Learning: Self-learning and flexible electronics through inherent component reconfiguration (more information).



5. CirroStrato: Synthesis and layout tools for IP protection based on reconfigurable transistors (more information).



6. Database System Acceleration on FPGAs (co-supervision of PhD student, 2019 - 2023)



7. SecuReFET: Secure Circuits through inherent Reconfigurable FET (more information).



8. DART: Design Automation for Reconfigurable Transistors (more information).


9. PRÄKLIMA FASSADE: Predictive self-learning facade design for smart energy buildings.




10. HANS: A framework for distributed ANN inference on heterogeneous edge devices.



11. SARA: Safety-Aware Relocation of functions in a multi-core computer Architecture.



12. Labview System-on-chip design methodology, 280,000 Euro, 2019.


13. Machine Learning for Fault Modelling in Chip Manufacturing (co-supervision of PhD student, 2020).


14. Design of Partially Reconfigurable Embedded Deep Learning Inference Accelerators (co-supervision of PhD student, since 2020).


15. Co-Design of Algorithms and Hardware for Low-Power Machine Learning Inference (co-supervision of PhD student, since 2020).


16. FPGA Floorplanner for partially reconfigurable systems, 103,500 Euro, 2016 (more information).



17. Digital Hardware for Approximate Computing of Deep Neural Networks (co-supervision of PhD student, since 2018).


18. Emulation platform for wildly heterogeneous chips, 40,000 Euro, 2017 (funded by Cfaed Cluster of Excellence, Orchestration seed grant).

19. Enabling very large-scale integration for novel materials, 45,000 Euro, 2016 (funded by Cfaed Cluster of Excellence, Orchestration seed grant).

Highlighted Collaborations

  1. Prof. Giovanni De Micheli, École Polytechnique Fédérale de Lausanne (EPFL, Switzerland): Logic Synthesis and Emerging Transistor Technologies.
  2. Prof. Henk Corporaal, Eindhoven University of Technology (TU/e, Netherland): Fault-Tolerant Reconfigurable Hardware Design, FPGA acceleration of Astronomy Applications.
  3. Prof. Muhammad Shafique, New York University Abu Dhabi (NYUAD, Dubai): Design of Approximate Functional Units for Reconfigurable Accelerators.
  4. Prof. Said Hamdioui, Delft University of Technology  (TU Delft, Netherland): In/Near Memory Computing Architectures.
  5. Prof. Sai Manoj Pudukotai Dinakarrao, George Mason University (GMU, USA): Approximate Processing In/Near Memory.
  6. Dr. Andre Guntoro, Robert Bosch GmbH (Germany): Cross-Layer Approximation of Neural Networks.
  7. Dr. Bernd Waschneck, Infineon (Germany): Co-Design of Algorithms and Reconfigurable Hardware for Embedded Machine Learning Accelerators.
  8. Dr. Tuan D. A. Nguyen, Xilinx (Singapore): Approximate Computing for Reconfigurable Accelerators, Cross-Layer Reliability of MPSoCs.
  9. Prof. Pierre - Emmanuel GAILLARDON, University of Utah (USA): Machine Learning for Logic Synthesis.
  10. Prof. Walter Weber, Vienna University of Technology (TU Wien, Austria): Design of Emerging Transistor Technologies.
  11. Dr. Farhad Merchant, RWTH Aachen University (Germany): Posit Arithmetic for Artificial Neural Network Design and Hardware Security.
  12. Prof. Kapil Ahuja, Indian Institute of Technology Indore (IIT Indore, India): Approximation of Neural Networks, From Circuit- to Application-Level.
  13. Prof. Santosh Kumar Vishvakarma, Indian Institute of Technology Indore (IIT Indore, India): CORDIC-Based Neuron Architecture Design for Neural Networks.
  14. Prof. Ozgur Sinanoglu, New York University Abu Dhabi (NYUAD, Dubai): Augmenting Security Through Emerging Reconfigurable Transistors.
  15. Prof. Rolf Drechsler, German Research Center for Artificial Intelligence (DFKI Bremen, Germany): Next Generation of IP Protection Through Reconfigurable Transistors.