Here is the list of domestic and international MSc/BSc theses and SHK/WHK Studentarbeit projects carried in our chair. You can find the available positions here.


  • Designing AI models for obstacle detection in pet robots using FPGA (Haroun Errachid Abbassi, National Institute of Applied Science and Technology, Tunisia).
  • New obfuscation scheme for thwarting ML-based attacks against Logic Locking (Zhentao Han, TU Dresden).
  • Exploring Technology Mapping using RL-Guided Runtime-Constrained Heuristics (Yash Richhariya, TU Dresden).
  • Designing Timing Attack Resilient RFET-based Circuits (Aniruddh Holemadlu, TU Dresden).
  • Simulating Power Attack Resilient RFET-based Circuits (Garvit Chhabra, TU Dresden).
  • Adversarially Robust and Efficient Neural Networks (Nilay Naharas, IIT Jammu, India).
  • Computationally efficient and robust deep learning models (Birla Institute of Technology and Science, India).
  • Robust and Efficient Deep Neural Network Models for Resource-limited Devices (David Silbermann, TU Dresden).
  • Application reliability improvement on FPGA platform (Jieyu Zhao, TU Dresden).
  • Finding optimum WCETs for mixed-criticality tasks using GNNs (Paul Justin, TU Dresden).
  • Hardware Assisted Federated Learning (Saul Isaac Sanchez Flores, TU Dresden).
  • Characterising RFET-based standard cells for circuit synthesis (Joram Brenz, TU Dresden).
  • Delay-Sensitivity of Reconfiguration Signals in Reconfigurable Standard Cells (Ludwig Pauly, TU Dresden).


  • Liberty File Generation (Joram Brenz, TU Dresden).
  • MISC-V: An FPGA-based emulation platform for RISC-V and Non-volatile Memories (Yuankang Zhao, TU Dresden).
  • FPGA-based Implementation of Time-to-Digital Converter for Quantum Key Distribution Systems (Qin Kun, TU Dresden).
  • Resource Efficient Neural Network Inference (Ipek Gecin, TU Dresden).
  • Programming for project tools, currently PRISM (Ludwig Pauly, TU Dresden).
  • Smart Coffee Machine (Nasri Mohamed Youssef, National Engineers School of Tunis ENIT).
  • Autonomous Robot Car Navigation Using Machine Learning (Nourchene Bargaoui, National Engineers School of Tunis).
  • Improving mapping approaches in AICs (Suraj Sathya Prakash, Birla Institute of Technology and Sciences, India).
  • Hardware Accelerators for Natural Language Processing Applications (Vishwas Gautam, BITS Pilani, India).
  • Design of AI/ML based Biomedical Signal Processing System (Tejas Dnyaneshwar Musale, Birla Institute of Technology and Science, India).
  • Machine-Learning (ML)-Based WCET Analysis in Mixed-Criticality Applications (Vikash Kumar, Indian Institute of Science).
  • Synthesizing FPGA based Approximate Operators with Generative Networks (Rohit Ranjan, Indian Institute of Technology Kharagpur).
  • Creating Physical LEF Library for RFET Standard Cells (Jorge Navarro Quijada,TU Dresden).
  • Reinforcement Learning Based Logic Synthesis (Yash Richhariya, ,TU Dresden).


  • Compiler Toolchains for Deep Learning Workloads on Embedded Platforms (Max Sponner, Infineon).
  • Light-Weight FPGA-Based Accelerator Design for Iris Recognition (Dennis Klar, TU Dresden).
  • High-Throughput Design of Approximate Operators in FPGAs (Muhammad Zaid, TU Dresden).
  • Energy efficiency optimizations on a CGRA using RFETs (Hasan Shakir, TU Dresden).
  • Parallel FPGA routing (Mohamed Bouaziz, TU Dresden/Università di Trento).
  • FPGA-based Artificial Neural Network Accelerator (Mohammad Naeim, TU Dresden/KU Leuven University).
  • Exploration of Cross-Layer Approximation for Artificial Neural Networks on FPGA (Balaji Venkataramana, BITS Pilani India).
  • Project Name: Data Flow Based Design Space Exploration for ANN Inference on Heterogeneous Edge Devices (Ansh Rupani, TU‌ Dresden)
  • Accelerated Hardware for ECG Pre-processing (Debabrata Chaudhury, BITS Pilani, Pilani, India)
  • Designing Deep Reinforcement Learning Architecture on FPGAs (Divyansh Choudhary, Indian Institute of Technology, Indore, India)
  • Deep Reinforcement Learning-based Control of Smart Energy Buildings (Nemath Ahmed, Indian Institute of Technology, Indore, India)
  • Exploring Machine Learning for Logic Synthesis (Yasasvi V. Peruvemba, Indian Institute of Technology).
  • Hardware Trojan design in CMOS and emerging nano-technologies (Desai Mohil Sandip, BITS Pilani India).
  • Neuromorphic computing using state-of-the-art components (Ishika Bhattacharya, BITS Pilani India).


  • Energy-Efficient CGRA Design for Bio-Signal Processing (Mohammad Aasim Ekhtiyar, TU Dresden).
  • Machine Learning in Heterogeneous IoT Distributed Network (Aditya Lohana, BITS Pilani India).
  • Implementation of energy-efficient DNNs for edge computing (Suresh Nambi, BITS Pilani, Pilani, India).
  • Deep Reinforcement Learning on FPGAs (Akhil Raj Baranwal, BITS Pilani, Hyderabad, India), Related paper 1, 2.
  • Cross-Layer Low Power Design for Heterogeneous Embedded Systems (Nisarg Sheth, BITS Pilani, India), Related paper.
  • Exploration of Prospects of Reconfigurable Nanotechnologies in Hardware Security (Abhiroop Bhattacharjee, BITS Pilani India).
  • Hyperdimensional Computing - A study of algorithms and hardware realizations (Vignesh Nagarajan, BITS Pilani India).


  • Evaluation of OpenCV based hardware accelerators on PYNQ framework running on Ultra96 board by implementing image processing applications (Mizanur Rahman, TU Dresden).
  • Architecture and CAD for Emerging Technologies (Pallab Nath, Indian Institute of Technology).
  • Low bit-width Quantization Schemes for DNNs (Siddharth Gupta, Indian Institute of Technology).


  • Approximate Signed Multiplier Blocks for FPGA (Hendrik Schmidl, TU Dresden).
  • Designing Reconfigurable Approximate Multipliers (Patil Siddhant Vitthal, 2018).
  • Hardware Trojan Design in Context of Emerging Reconfigurable Nanotechnology (Dipika Badri, BITS Pilani India).
  • Neural Network Design on FPGA (Namrata Chakka, India Vellore Institute of Technology).


  • Designing Reconfigurable Approximate Arithmetic Architecture on FPGA (Markus Krause, TU Dresden).
  • Physical Synthesis and Design For Reconfigurable Transistors (Ansh Rupani, TU Dresden).
  • Multi-processor Emulation Platform on FPGA (Sanjeev Sripadraj Murthy, BITS Pilani India).
  • Emulation Platform for Wildly Heterogeneous Chips (Divya Jain, BITS Pilani India).
  • Buil-in Self-test for FPGA designs (Kshitij Shrivastava, BITS Pilani, Hyderabad, India).