Preliminary Program

This year, the 31st edition of FPL will be celebrated virtually. The main conference will take place from 1 Sept until 3 Sept, 2021. The workshops and tutorials will be organized from 30 Aug until 31 Aug, 2021.

The preliminary program of the main conference can be accessed here.

Workshops and Tutorials

  • Introduction to the Xilinx Kria SOM with PYNQ

The Kria portfolio of adaptive system-on-modules (SOMs) are production-ready small form factor embedded boards that enable rapid deployment in edge-based applications. Coupled with a complete software stack and pre-built, production-grade accelerated applications, Kria adaptive SOMs are a new method of bringing adaptive computing to AI and software developers. This tutorial will introduce the new Xilinx Kria portfolio and the Kria Vision kit development platform and demonstrate how it can be used with PYNQ, an open-source Python and Jupyter framework for Xilinx platforms.

 

  • Software-Defined Hardware: Digital Design in the 21st Century with Chisel

To develop future more complex digital circuits in less time we need a better hardware description language than VHDL or Verilog. Chisel is a hardware construction language intended to speed up the development of digital hardware and hardware generators.

Chisel is a hardware construction language implemented as a domain-specific language in Scala. Therefore, the full power of a modern programming language is available to describe hardware and, more important, hardware generators. Chisel has been developed at UC Berkeley and successfully used for several tape outs of RISC-V by UC Berkeley students and a chip for a tensor processing unit by Google. Here at the Technical University of Denmark we use Chisel in the T-CREST project and in teaching digital electronics and advanced computer architecture.

In this tutorial we will give an overview of Chisel to describe circuits, how to use the Chisel tester functionality to test and simulate digital circuits, present how to synthesize circuits for an FPGA, and present advanced functionality of Chisel for the description of circuit generators.

The aim of the course is to get a basic understanding of a modern hardware description language and be able to describe simple circuits in Chisel. This course will give a basis to explore more advanced concepts of circuit generators written in Chisel/Scala. The intended audience is hardware designers with some background in VHDL or Verilog, but Chisel is also a good entry language for software programmers entering into hardware design (e.g., porting software algorithms to FPGAs for speedup).

 

  • Workshop on DevOps Support for Cloud FPGA platforms (cFDevOps)

Organizers: Chris Kachris (inaccel), Christoph Hagleitner (IBM Research Europe), Christian Plessl (Paderborn Center for Parallel Computing), Dionysios Diamantopoulos (IBM Research Europe), Burkhard Ringlein (IBM Research Europe)

Abstract: With the slowdown of Moore's law as we know it, the Cloud is resorting to heterogeneous, accelerated computing to satisfy the ever-increasing demand for performance and power efficiency. In just a few years, FPGAs have emerged as compute accelerators next to GPUs and are part of the standard offerings from many Cloud vendors. However, the development environment, deployment procedures, security measures, and monitoring tools are different for each platform and the portability of the FPGA kernel designs remains limited.

In this workshop, leading platform providers, designers of development environments, and developers are going to present the state-of-the-art for Cloud FPGA platforms and explore opportunities and directions for future improvements from the developer's point of view. Instead of focusing on the performance and optimization of a specific application, the goal of this workshop is to highlight the challenges, which a Cloud application developer faces when designing, implementing, deploying, scaling and debugging Cloud services on Cloud FPGA platforms. A focus area for this years edition are end-to-end toolchains, compilation and debugging tools for heterogeneous platforms.

 

  • Workshop on Reconfigurable Computing for Machine Learning – RC4ML’2021