Jiahong Bi




Visitor's Address


+49 (0)351 463 43726

+49 (0)351 463 39995

Helmholtzstrasse 18, BAR III60

Curriculum Vitae

Jiahong Bi received his Bachelor degree in Computer Science and Technology from Xidian University, China in June 2019, and his Master degree in CS from TU Dresden in December 2023. His Master Thesis is finished at the Chair for Compiler Construction, focusing on implementing and evaluating a custom FPGA back-end for a data flow model MLIR dialect, which utilizes High-Level Synthesis by CIRCT project and several AMD Xilinx tools.

Jiahong finished his research project at CCC in January 2023, then continued working as a research student till April 2023. Jiahong did research work with Chair of Adaptive Dynamic System from 2022 to 2023 as well, from which he gained knowledge of FPGA hardware and HLS technology. After these Jiahong joined the chair as research assistant in February 2024, where he will work on project “MYRTUS: Multi-layer 360° dYnamic orchestrion and interopeRable design environmenT for compute-continUum Systems”, including defining novel programming methods and compiler infrastructures to deploy optimized software onto heterogeneous computing systems in both the embedded and high-performance computing domains.


  • 2023

  • Jiahong Bi, "A Lowering for High-Level Data Flows to Reconfigurable Hardware", Master's thesis, TU Dresden, Dec 2023. [Bibtex & Downloads]
  • Karl F. A. Friebel, Jiahong Bi, Jeronimo Castrillon, "BASE2: An IR for Binary Numeral Types", In Proceeding: 13th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART 2023), Association for Computing Machinery, pp. 19–26, New York, NY, USA, Jun 2023. [doi] [Bibtex & Downloads]