Hamid Farzaneh




Visitor's Address


+49 (0)351 463 43729

+49 (0)351 463 39995

Helmholtzstrasse 18,3rd floor, BAR III55

01069 Dresden

Curriculum Vitae

Hamid Farzaneh received his bachelor's degree in Computer Engineering from Shiraz University in August 2019, and his master's degree in Computer Systems and Architecture from Shahid Beheshti University in November 2021.

In August 2022, he joined the chair as a research assistant. He works on high-level compiler frameworks (like MLIR) and optimization for data and computation mapping onto highly heterogeneous systems with mainstream CPUs, FPGAs, SRAM, DRAM, and emerging NVMs and accelerators.

Student Topics

The volume of data processing in these applications has skyrocketed in recent years and demands significantly higher off-chip memory bandwidth. However, increasing the off-chip bandwidth is becoming increasingly expensive and is strictly constrained by the chip package and system models. To overcome the memory wall and capacity and power walls, computer architects are moving to non-Von-Neumann system models like near-memory and in-memory computing. However, The programmability aspect of these systems has received relatively less attention. Using the power of compilers, I tackle issues in high performance, energy efficiency, and hardware/software cooperation of these systems.

In that regard, my current main topics are:

  • Working on high-level compiler frameworks (like MLIR) and optimizing data and computation mapping for data and computation mapping onto heterogeneous systems
  • Developing models for managing workloads in heterogeneous systems

Possible student topics include:

  • Front-ends for MLIR Computing-in-Memory(CIM) Compiler

End-to-end compilation flows for CIM-capable systems exist, but interfaces to high-level languages are missing (limited). The goal of this project is to design and implement front-ends to enable lowering high-level languages/descriptions to the CIM compilers.

  • Heterogeneous Systems: Mapping and Optimizations
Future systems are predicted to be highly heterogenous, and efficient mapping and optimizations of the application on a heterogenous system are central to the system’s performance. This project aims to design an MLIR-based automatic infrastructure to map kernels to the fitting hardware target and optimize for it.

Also, if you have a related topic in mind, please feel free to reach out.


  • 2024

  • João Paulo C. de Lima, Asif Ali Khan, Hamid Farzaneh, Jeronimo Castrillon, "Full-Stack Optimization for CAM-Only DNN Inference" (to appear), Proceedings of the 2024 Design, Automation and Test in Europe Conference (DATE), IEEE, pp. 1-6, Mar 2024. [Bibtex & Downloads]
  • 2023

  • Jörg Henkel, Lokesh Siddhu, Lars Bauer, Jürgen Teich, Stefan Wildermann, Mehdi Tahoori, Mahta Mayahinia, Jeronimo Castrillon, Asif Ali Khan, Hamid Farzaneh, João Paulo C. de Lima, Jian-Jia Chen, Christian Hakert, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng, "Special Session – Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications" (to appear), Proceedings of the 2023 International Conference on Compilers, Architecture, and Synthesis of Embedded Systems (CASES), Sep 2023. [Bibtex & Downloads]
  • João Paulo C. de Lima, Asif Ali Khan, Hamid Farzaneh, Jeronimo Castrillon, "Efficient Associative Processing with RTM-TCAMs", In Proceeding: 1st in-Memory Architectures and Computing Applications Workshop (iMACAW), co-located with the 60th Design Automation Conference (DAC'23), 2pp, Jul 2023. [Bibtex & Downloads]
  • Asif Ali Khan, Hamid Farzaneh, Karl F. A. Friebel, Clément Fournier, Lorenzo Chelini, Jeronimo Castrillon, "CINM (Cinnamon): A Compilation Infrastructure for Heterogeneous Compute In-Memory and Compute Near-Memory Paradigms", arXiv, Jan 2023. [doi] [Bibtex & Downloads]