Robert Khasanov

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E-mail

Phone

Fax

Visitor's Address

robert.khasanov@tu-dresden.de

+49 (0)351 463 39978

+49 (0)351 463 39995

Helmholtzstrasse 18
3rd floor, Room BAR III 58
01069 Dresden
Germany

Curriculum Vitae

Robert Khasanov has received his Bachelor's and Master’s degree in Computer Science from Moscow Institute of Physics and Technology in 2012 and 2014 respectively.  During the study, he also held positions at Intel where he was working on optimising binary translator system, and then in LLVM compiler project. In 2015 Robert carried out an internship at Scalable Parallel Computing Lab (ETH Zurich) where he was working on optimal data replication in fault tolerant distributed databases. Currently, Robert is a Ph.D. student at the Chair for Compiler Construction. In his studies, he works on language support and optimizations for energy-efficient execution of multiple applications on emerging systems. Key interests include dataflow languages with implicit and explicit parallelism, compiler-runtime interaction, and energy optimizations.

Student Thesis Topics

At the Chair for Compiler Construction, we are developing a hybrid system called TETRiS, which aims at energy-efficient and predictable execution of multiple applications. The system exploits inherited symmetries in hardware and software to reduce the design space exploration. The approach consists of two parts, at design-time, the set of Pareto-optimal configurations is generated, and then depending on the current workload, the configurations are selected and transformed at runtime.

Possible project topics include:

  • Runtime adaptivity of Kahn Process Networks with implicit parallelism

Kahn process networks (KPN) are an abstraction for modeling computation which makes communication patterns explicit. An extension of implicit parallelism for KPN allows applications to change the number of used resources at runtime in a malleable way, which allows applications to adapt to the changes in the environment and, therefore, achieve better energy efficiency. In this project, you will develop this application model in the Mocasin framework, extending the hybrid methodology for this class of applications.

  • Frequency scaling in hybrid mapping methodology

Dynamic Voltage Frequency Scaling (DVFS) allows reducing the energy consumption of the system further. A naive approach to adapt DVFS in the hybrid methodology would be to generate the operating points for each available frequency configuration of the platform. This, however, would lead to a blow-up of operating points and a complex runtime algorithm. In this research project, you will develop an interplay of the hybrid methodology with frequency scaling.

  • A hybrid approach for mixed-critical applications

In this work, you will refine the hybrid methodology approach for non-real-time application and mixed-criticality applications.

  • Runtime scheduling in Linux

In this work, you will develop the runtime algorithm in the prototype in C++ for scheduling applications running on Linux.

This list is open-ended. Feel free to approach me and discuss these or other ideas.

If you are interested, please contact me by email.

Publications

  • 2021

  • Robert Khasanov, Julian Robledo, Christian Menard, Andres Goens, Jeronimo Castrillon, "Domain-specific hybrid mapping for energy-efficient baseband processing in wireless networks", In ACM Transactions on Embedded Computing Systems (TECS). Special issue of the International Conference on Compilers, Architecture, and Synthesis of Embedded Systems (CASES), Association for Computing Machinery, vol. 20, no. 5s, New York, NY, USA, Sep 2021. [doi] [Bibtex & Downloads]
  • Christian Menard, Andrés Goens, Gerald Hempel, Robert Khasanov, Julian Robledo, Felix Teweleitt, Jeronimo Castrillon, "Mocasin—Rapid Prototyping of Rapid Prototyping Tools: A Framework for Exploring New Approaches in Mapping Software to Heterogeneous Multi-cores", Proceedings of the 2021 Drone Systems Engineering and Rapid Simulation and Performance Evaluation: Methods and Tools, co-located with 16th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), Association for Computing Machinery, pp. 66–73, New York, NY, USA, Jan 2021. (Video Presentation) [doi] [Bibtex & Downloads]
  • 2020

  • Robert Khasanov, Jeronimo Castrillon, "Energy-efficient Runtime Resource Management for Adaptable Multi-application Mapping", Proceedings of the 2020 Design, Automation and Test in Europe Conference (DATE), IEEE, pp. 909–914, Mar 2020. (Best paper award candidate E-Track, Video Presentation) [doi] [Bibtex & Downloads]
  • 2018

  • Robert Khasanov, Andrés Goens, Jeronimo Castrillon, "Implicit Data-Parallelism in Kahn Process Networks: Bridging the MacQueen Gap", Proceedings of the 9th Workshop and 7th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms (PARMA-DITAM'18), co-located with 13th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC), ACM, pp. 20–25, New York, NY, USA, Jan 2018. [doi] [Bibtex & Downloads]
  • 2017

  • Andrés Goens, Robert Khasanov, Marcus Hähnel, Till Smejkal, Hermann Härtig, Jeronimo Castrillon, "TETRiS: a Multi-Application Run-Time System for Predictable Execution of Static Mappings", Proceedings of the 20th International Workshop on Software and Compilers for Embedded Systems (SCOPES'17), ACM, pp. 11–20, New York, NY, USA, Jun 2017. [doi] [Bibtex & Downloads]
  • Markus Haehnel, Frehiwot Melak Arega, Waltenegus Dargie, Robert Khasanov, Jeronimo Castrillon, "Application Interference Analysis: Towards Energy-efficient Workload Management on Heterogeneous Micro-Server Architectures", Proceedings of the 7th International Workshop on Big Data in Cloud Performance (DCPerf'17), IEEE Conference on Computer Communications Workshops (INFOCOM WKSHPS), pp. 432-437, May 2017. [doi] [Bibtex & Downloads]
  • 2016

  • Andres Goens, Robert Khasanov, Jeronimo Castrillon, Simon Polstra, Andy Pimentel, "Why Comparing System-level MPSoC Mapping Approaches is Difficult: a Case Study", Proceedings of the IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC-16), pp. 281-288, Ecole Centrale de Lyon, Lyon, France, Sep 2016. [doi] [Bibtex & Downloads]