In the Chair for Compiler Construction we are interested in optimization methods, in general. This includes traditional compiler optimizations, optimizations for programs written as dataflow and process networks, optimizations for energy efficiency (e.g., in the HAEC project), optimization for domain-specific languages and for new emerging technologies. As such, this research line permeates all projects performed at the chair.
Applications are commonly optimized for execution speed, memory footprint, or binary size. Current hardware trends force us to adopt other, less traditional optimization targets, in particular power consumption and reliability.
Present-day CPUs are complex systems (Figure 1), with many components such as caches or FPU dedicated to improving execution speed. In the future, wildly heterogeneous processor systems will become more pervasive, leading to even more complex chip designs. Managing heterogeneous systems is a complicated problem: for example, tight power budgets may require that some chip components be switched off from time to time, leading to dark silicon [1,2]. Performance engineers therefore need tools that enable simultaneous profiling and optimizing of power consumption and execution speed.
Instead of fully switching off individual chip components, chips can be run below their nominal supply voltage. This is known as near-threshold computing or dim silicon, which generally renders computations unreliable. Another source of unreliability is process variation as hardware is manufactured at ever shrinking feature sizes (Figure 2). Unreliable execution may be acceptable for parts of applications. For example, Figure 3 shows the vulnerability of individual instructions in an application. Less vulnerable sections can be executed on unreliable hardware to save power or speed up execution. More critical sections will have to be executed on reliable hardware. Once again, performance engineers need tools to analyze the trade-off between reliability and energy consumption or execution speed.
There are many aspects to reliability-related research (see Resilience Path). Our main focus is on creating a reliability and energy-aware software stack, which includes
- compiling applications for execution on unreliable hardware [6,7],
- hardening critical operating-system code against hardware faults,
- methods and languages for specifying reliability and energy consumption requirements [4,5],
- program analyses to identify reliability-critical sections of applications.
 G. Venkatesh et al., "Conservation cores: reducing the energy of mature computations", in 15th Symposium on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 205–218, 2010. [doi]
 H. Esmaeilzadeh et al., "Dark silicon and the end of multicore scaling", in 38th International Symposium on Computer Architecture (ISCA), pages 365 –376, 2011. [pdf]
 M. Shafique, S. Garg, D. Marculescu, J. Henkel, "The EDA Challenges in the Dark Silicon Era", in 51st IEEE/ACM/EDAA Design Automation Conference (DAC), 2014.
 A Sampson, A Baixo, B Ransford, T Moreau, J Yip, L Ceze, and M Oskin, Accept: A programmer-guided compiler framework for practical approximate computing, 2015. [pdf]
 M Carbin, S Misailovic, and M C Rinard, Verifying quantitative reliability for programs that execute on unreliable hardware, Proceedings of the 2013 ACM SIGPLAN international conference on Object oriented programming systems languages & applications (New York, NY, USA), OOPSLA’13, ACM, October 2013, pp. 33–52. [pdf]
 N A. Rink, D Kuvaiskii, J Castrillon, C Fetzer,"Compiling for Resilience: the Performance Gap", Chapter in Parallel Computing: On the Road to Exascale (ParCo 2015). Extended from Proceedings of the Mini-Symposium on Energy and Resilience in Parallel Programming (ERPP 2015) (Gerhard R. Joubert, Hugh Leather, Mark Parsons, Frans Peters, Mark Sawyer, eds.), IOS Press, vol. 27, pp. 721–730, Edinburgh, Scotland, sep 2015 [doi]
 Norman A. Rink, Jeronimo Castrillon, "Improving Code Generation for Software-based Error Detection", Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES), co-located with ESWEEK 2015, pp. 16–30, Amsterdam, The Netherlands, oct 2015. [pdf]